A Simple Approach to Uncover Thread-level Parallelism on a Simultaneous Multithreaded Processor
Authors: Fredrik Warg and Per Stenström

As chip multiprocessors with simultaneous multithreaded cores are becoming commonplace, there is a need for simple approaches to exploit thread-level parallelism. In this paper, we consider thread-level speculation as a means to reap thread-level parallelism out of application binaries. We first investigate the tradeoffs between scheduling speculative threads on the same core and on different cores. While threads contend for the same resources using the former approach, the latter approach is plagued by the overhead for inter-core communication. Despite the impact of resource contention, our detailed simulations show that the first approach provides the best performance due to lower inter-thread communication cost. The key contribution of the paper is the proposed design and evaluation of the dual-thread speculation system. This design point has very low complexity and reaps most of the gains of a system.

Keywords: Multiprocessors, chip-multiprocessors, thread-level speculation, module-level parallelism, misspeculation prediction, performance evaluation, dual-thread speculation.
Fulltext: Available at SpringerLink
Published: International Journal of Parallel Programming (IJPP), pages 166-183, Volume 36, Number 2, April 2008.
DOI: 10.1007/s10766-007-0064-z
Note: if you are unable to get access to the article, the results are also available in chapters 8-9 in my thesis (though presented differently in text and figures).

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